Analog IC Layout Design Internship

vor 2 Wochen

Munich, Bayern, Deutschland Renesas Electronics Vollzeit

Renesas Electronics is seeking a highly motivated and talented Intern / Working Student / (F/M/D) to join our esteemed Analog Layout Design Team.

In this role, you will contribute to the development of cutting-edge analog integrated circuits by applying your expertise in layout design and verification. You will collaborate closely with a team of experienced engineers to ensure the successful delivery of projects.

Responsibilities:
  • Participate in the design process, working alongside layout and circuit design engineers to resolve technical challenges and ensure high-quality layouts.
  • Utilize industry-standard Electronic Design Automation (EDA) tools such as Cadence and Synopsys for layout creation, editing, and verification at both cell and block levels.
  • Implement state-of-the-art layout techniques to optimize matching, ESD protection, latch-up prevention, and parasitic reduction. Demonstrate a thorough understanding of the fabrication process from a physical perspective.
  • Actively engage in project meetings, providing regular updates on progress and identifying potential timescale risks.
  • Where applicable, leverage schematic-driven layout methodologies and explore top-level auto routing techniques.
  • Contribute to review sessions and prepare comprehensive documentation and data for wafer tape-out.
Qualifications:
  • Pursuing a degree in Electrical/Electronic Engineering, Physics, Computer Science, or a related field.
  • Possess excellent verbal and written communication skills in English.
  • Demonstrate a strong understanding of integrated analog circuit design principles.
  • Have a solid grasp of chip layout concepts, including cell and block level creation, editing, and full verification.
  • Exhibit a highly self-motivated and adaptable work ethic.
  • Possess foundational knowledge of CMOS devices, including high voltage operation, and the ability to interpret design manuals effectively.
Nice-to-Have Skills:
  • Experience with layout techniques for matching, ESD protection, latch-up prevention, and parasitic reduction.
  • Prior experience in analog IC/mixed-signal IC layout design and verification. Ability to contribute innovative ideas for chip size reduction.

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