Analog IC Layout Design Trainee
vor 3 Wochen
Job Overview
We are seeking a dedicated Intern / Working Student / (F/M/D) to join our Analog Layout Design Team.
Key Responsibilities:
Collaborate with layout and circuit design engineers to deliver projects and address any technical challenges that may impact layout quality. Employ EDA tools (Cadence and Synopsys) for layout design and all associated verification tasks, executing layout activities at both cell and block levels, including editing and comprehensive verification. Implement advanced layout techniques for matching, ESD, latch-up prevention, and parasitic reduction, while maintaining a strong understanding of the physical processes involved. Participate in relevant project meetings, continuously assess and report on potential risks to timelines. Where feasible, utilize schematic-driven layout and consider top-level auto-routing options. Engage in review sessions and prepare all necessary documentation and data for wafer tape-out.OUR OFFER
Close collaboration with your mentor Flexible working hours Flat organizational structure Interaction with international teams Convenient public transportation access Competitive compensation QualificationsCurrently pursuing a degree in Electrical/Electronic Engineering, Physics, Computer Science, or related disciplines. Strong verbal and written communication skills in English are essential. Solid understanding of integrated analog circuit design principles. Familiarity with chip layout processes at both cell and block levels, including editing and full verification. Highly self-motivated and adaptable to new challenges. Basic knowledge of CMOS devices, including high voltage, and the ability to interpret Design Manuals.
Preferred Qualifications:
Experience with layout techniques for matching, ESD, latch-up prevention, and parasitic reduction, with a strong understanding of the physical processes involved. Background in analog IC/mixed-signal IC layout design and verification, with the ability to contribute ideas for chip size optimization. Company OverviewRenesas is recognized as one of the leading global semiconductor companies. We are committed to developing a safer, healthier, greener, and smarter world, aiming to make every endpoint intelligent through our product solutions in automotive, industrial, infrastructure, and IoT markets. Our extensive product portfolio includes world-class MCUs, SoCs, analog and power products, as well as Winning Combination solutions that integrate these complementary offerings. We are a vital supplier to the world's foremost electronics manufacturers; while our products may not always be visible, they are integral to everyday life.
With approximately 21,000 employees across more than 30 countries, Renesas fosters a global team culture that embodies our guiding principles: Transparency, Agility, Global Reach, Innovation, and Entrepreneurship. We are dedicated to diversity and inclusion, supported by initiatives and a leadership team committed to these values. At Renesas, we aspire to create a sustainable future where technology enhances our lives. Be part of the next chapter in electronics and the world.
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