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Senior Engineer in Digital Design Verification

vor 3 Monaten

Munich, Bayern, Deutschland Albelissa Vollzeit

Position Overview

Albelissa is seeking a talented and experienced professional for the role of:

Senior Digital Design Verification Engineer

Key Responsibilities

  • Develop and implement verification strategies for digital and mixed-signal intellectual properties (IPs) in alignment with system specifications. Design testbench architecture, create verification plans, and collaborate with design engineers across digital, mixed-signal, and analog domains for effective feature extraction.
  • Utilize advanced methodologies such as UVM and Formal Verification to construct efficient and reusable verification environments and testbench components. Create both IP-level and system-level testbenches to maximize coverage and reusability. Generate constraint random tests, checkers, and coverage models based on integrated circuit specifications.
  • Establish infrastructure to facilitate mixed-signal verification and analog/real-number behavioral modeling.
  • Oversee the execution of verification plans, which includes setting up environments, running regressions (RTL and gate-level), collecting coverage data, and debugging failures.
  • Facilitate technical communication with clients and other project teams, including participation in design reviews, defining test requirements, tracking progress, and engaging in problem-solving.
  • Provide mentorship to junior engineers, helping them acquire the necessary knowledge and experience through hands-on project work.

Qualifications

  • A Master's degree in Electrical Engineering with a minimum of 7 years of relevant experience, or a Bachelor's degree with at least 10 years of experience, focusing on Digital Verification or a related field.
  • Proven expertise and leadership in digital verification, including testbench architecture and the planning and execution of digital and mixed-signal designs.
  • In-depth knowledge of block-level and top-level verification of integrated systems, with an emphasis on reusable components and coverage models.
  • Proficiency in SystemVerilog for verification, utilizing advanced methodologies such as UVM, SVA, or similar techniques, including constrained random and metric-driven verification.
  • Familiarity with Formal verification processes.
  • Experience with electronic design automation (EDA) tools for simulation, regression, feature extraction, and verification planning. The ability to automate verification tasks is advantageous.
  • Knowledge of System Verilog RNM and analog behavioral modeling.
  • Understanding of digital design and analog methodologies is beneficial.
  • Proficiency in scripting languages such as Python, Tcl, or Perl for automation and code generation.
  • Fluency in English is required.
  • Strong team player with a calm professional demeanor, excellent listening skills, and the ability to prioritize and organize work effectively.

Required Skills

  • University degree in Electrical Engineering with 7+ years of experience or a Bachelor's degree with 10+ years of experience.
  • Emphasis on Digital Verification, testbench architecture, and verification planning.
  • Experience with digital and mixed-signal designs, block-level and integrated systems verification.
  • Proficiency in SystemVerilog (UVM, SVA, or similar), including constrained random and metric-driven verification.
  • Familiarity with Formal verification and EDA tools.
  • Knowledge of System Verilog RNM and analog modeling.
  • Scripting skills in Python, Tcl, or Perl.
  • Fluency in English.
  • EU citizenship or valid work permit is preferred.