ASIC Digital Design Engineer Senior

vor 3 Wochen

Munich, Bayern, Deutschland Synopsys Vollzeit
Job Description and Requirements

The Senior ASIC Design Engineer is responsible for generating and verifying high-quality RTL design for the Synopsys High Speed Ethernet DesignWare IP. The work involves block and function definition, detailed specification, RTL coding, and code verification.

Key Responsibilities:
  • Collaborate with the Design and Verification Team to write test plans, troubleshoot RTL code, and support Lint, CDC, Synthesis, and physical design activities.
  • Develop and maintain knowledge of RTL Verilog and System Verilog Language, coding, and code simulation techniques.
  • Experience in Ethernet system design and knowledge of UVM to support the Design Verification Team.
Requirements:
  • Excellent knowledge in RTL Verilog and System Verilog Language, coding, and code simulation techniques.
  • Experience in Ethernet system design.
  • Knowledge of UVM required to support the Design Verification Team.
About Synopsys

Synopsys is at the heart of the innovations that change the way we work and play. We're powering the Era of Smart Everything with the world's most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

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