Student (M/F/d): Layout Strategies for Capacitive

Vor 2 Tagen

Ilmenau, Deutschland IMMS Institut für Mikroelektronik- und Mechatronik-Systeme gemeinnützige GmbH (IMMS GmbH) Vollzeit

During your studies, you can contribute to our ongoing research projects. Join us in pushing the limits of what is technically feasible and be part of breaking new ground together. We offer a variety of challenging and practice-oriented topics for mandatory internships, Bachelor’s or Master’s theses or for student research assistants. You will analyse important scientific preliminary questions and support the project teams with development activities.
**Place of work**: Erfurt
**Team**: Microelectronics
**Career level**: Mandatory Internship, Thesis
**Research field**: Integrated sensor systems
**Time scope**: 3-6 months
**Start**: As soon as possible
**Application deadline**: 2024-12-31
**Reference number**: IMMS_STUD_ME_0924
SAR ADCs are a type of analog-to-digital converters which determine the output value by successive approximation of the input voltage with a DAC that is controlled by the SAR logic. In most cases, this DAC is realized by a binary weighted capacitor array. Within this array, there is one switched capacitor for each bit of resolution. The capacitance values are binary multiples of each other and their ratios need to be very accurate. Creating a layout which provides such a high accuracy of the capacitance ratios is a challenging task due to multiple undesired effects like parasitic capacitances.
This work shall focus on different layout strategies for capacitive DAC arrays in order to keep the inaccuracy caused by parasitic capacitances and mismatch as small as possible. There are many ways of placing the capacitors and routing between them. For a given circuit, various layout patterns shall be applied, analyzed and compared to each other. The analysis will be done by post-layout simulation with extracted parasitic elements. The goal is to find good placement and routing patterns in terms of matching and parasitic effects.
Additionally, these insights shall contribute to the development and improvement of an automated layout generation tool. It can generate the layout of certain structures like capacitor arrays according to the implemented layout pattern and the settings. The layout strategies being explored in this work need to be generalized so that they can be applied to DAC arrays of any size. As a last step, the layout process shall be put into a procedural description so that a software engineer would be able to implement it.
**WHAT TO DO**:

- Familiarisation with the topic and the layout tools
- Creation of layouts with various alignment and routing patterns for a reference circuit (manually and using a layout generator)
- Analysis of parasitic effects and mismatch by running extracted simulations
- Comparison of the different layout strategies
- Generalisation and algorithmic description of favorable layout strategies

**WHAT TO BRING WITH YOU**:

- advanced studies in the field of electrical engineering
- Knowledge of analog CMOS circuit technology
- motivated and self-driven way of working

**AND THIS IS US**:
WE ARE LOOKING FORWARD TO MEETING YOU
We thank you for your interest in working with us.
**WHAT CAN WE OFFER YOU**:

- An attractive workplace in a modern, very well-equipped and industry-oriented research institute
- Work directly at the interface between university and industry
- Work in a flexible and creative team and on innovative and challenging topics

**Address**:
IMMS Institut für Mikroelektronik
- und Mechatronik-Systeme gemeinnützige GmbH (IMMS GmbH)
Ehrenbergstraße 27
98693 Ilmenau
Germany
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