Senior Digital Designer

**Current openings;**

**Senior Digital Designer & Senior Design Verification - Europe onsite (Germany-Hamburg)**

Following is the requirement for **Europe onsite (Germany
- Hamburg)**:
**Required Experience**: 5+ Years experience

**1. Senior Digital Designer (2 positions )**:Immediate joiners are preferred.

**Responsibilities**
- Contribute to the micro-architecture, RTL design, and integration of a System on Chip (SoC) or SoC sub-system, from requirements specification to tape-out and beyond
- Develop and deliver signed-off Verilog RTL and associated deliverables (e.g., clock/reset domain constraints, timing constraints, design documentation)
- Model and elaborate abstractions that enable pre-silicon simulations of your design using industry CAD tools
- Analyze, compare, and select different circuit topologies for optimal design
- Optimize the performance, power, area, and timing of your design according to requirements and constraints established by IC SoC Product architects
- Collaborate with various teams such as Architecture, Verification, FPGA Design, DFT, Physical Implementation, Silicon Validation, etc., to achieve high-quality silicon products and meet
- Schedule objectives
- Resolve problems using knowledge in several areas, including: Digital signal processing architecture and design, FPGA tooling and design,Clock and reset infrastructure, On-chip interconnect and interfaces, ARM CPU/MCU and DSP architectures, Design for low power and UPF modeling, Functional safety applied to digital SoC design, Requirements engineering and related tools, Programming in Matlab/Simulink, and scripting languages like Python or Perl

**Profile**
- Digital IP or SoC design engineer with experience in all aspects of RTL design flow i.e. from specification to micro-architecture, RTL design, verification, timing analysis, area/power estimation and DFT concepts
- Strong experience in RTL design, digital signal processing, SoC integration, RTL signoff tools (Synthesis/CDC/RDC/Lint)
- Basic knowledge of compute core (ARM or RISC-V) / DSP architectures as well as ARM-Amba bus protocols would be considered a plus
- Proven experience with automation using several programming and scripting languages
- Fluent written and verbal communication in English
- M.Sc. or PhD. Degree in Electrical Engineering or Computer Science.

**2. Senior Design Verification (2 positions )**:Immediate joiners are preferred.

**Responsibilities**
- Responsible for defining and writing verification plans based on requirements documents
- Define verification strategy according to design specification documents
- Responsible for architecting and developing UVM- and software-based verification environments for RTL simulation
- Define and develop test cases within an appropriate verification framework
- Create stimulus and assertions, run simulations, and debug test cases on design models (RTL, Gate level, Emulation platform)
- Run regressions, collect, and analyze code/functional coverage
- Provide guidance and support to verification engineers

**Profile**
- Proven experience in testbench design and development using UVM methodology for IP/Subsystem/SoCs
- Proven experience in verification sign-off at IP/Sub System/SoC level with test plan development, functional & code coverage analysis
- Proven experience in EDA tools from Cadence (Xcelium, Simvision, Verisium, vManager, Jasper) and / or Synopsys (VCS, Verdi)
- Understanding of software development for embedded CPUs, and experience in developing and debugging software
- Basic experience in execution of Gate Level Netlist simulation with back-annotated timing / Basic experience on writing System Verilog assertions / Basic understanding of Formal flow /methodologies
- Ability to question and identify weaknesses in specifications, tool environments, etc.
- Pro-active attituded engineer with proven experience in digital IP & SoC verification & good communication skills
- Fluency in English language.
- M.Sc. Degree in Electrical Engineering or Computer Science, with 5+ years of experience on IP/Sub-System/SoC Verification