Design Verification Engineer
vor 16 Stunden
We are seeking a highly skilled Design Verification Engineer to join our Advanced Mixed-Signal (AMS) team at Apple. As a key member of our team, you will be responsible for designing and developing verification environments for complex multi-layer systems using the SystemVerilog UVM library.
Key Responsibilities- Develop and execute verification strategies to ensure bug-free tape-outs
- Design and implement performance-based analysis and power-related analysis
- Deliver test cases for design for test and test engineering teams
- Conduct gate-level verification (power and timing) and lab bring-up support
- Strong knowledge of SystemVerilog test-bench language and UVM
- Hands-on experience with constrained random verification environments
- Basic design background for verification results analysis
- Proficiency in Object Oriented Programming (OOP)
- Proficiency in English language
- Master's degree or PhD in Electrical/Computer Engineering or equivalent
- Hands-on experience with Assertion Based Verification
- Familiarity with system design using C++, Python, or Verilog
- Familiarity with FPGA emulation platforms
Apple is an Equal Opportunity Employer committed to diversity and inclusion. We strive to create an environment where everyone can thrive and contribute to our mission to innovate and make a positive impact on the world.
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