Senior ASIC Design Verification Expert

vor 5 Stunden

Munich, Bayern, Deutschland Siemens Industry Software Sp. Z o.o. Vollzeit
About the Role

We are Siemens Industry Software Sp. Z o.o., a global technology leader in electronic design automation software.

Job Overview

This is an exciting opportunity for a skilled Senior ASIC Design Verification Expert to join our growing team at Tessent Embedded Analytics, where you will play a key role in verifying silicon IP and driving innovation in digital design verification.

What You'll Be Doing
  • Design Verification Planning: Develop comprehensive verification plans from devising a verification strategy through to coverage closure, ensuring thorough understanding of design specifications.
  • Collaboration: Work closely with design and architecture teams to understand design requirements and develop verification strategies, fostering open communication and knowledge sharing.
  • Tool Access and Influence: Leverage advanced tools and opportunities to influence the features of Mentor verification tools, driving continuous improvement and staying up-to-date with industry trends.
  • Detailed Verification Plans: Create and execute detailed verification plans for ASIC designs, guaranteeing comprehensive coverage of all design features and functionalities.
  • Testbench Development: Design and maintain reusable, scalable, and robust testbenches using industry-standard verification languages and methodologies (e.g., SystemVerilog, UVM).
  • Debugging and Resolution: Identify, analyze, and debug design issues, working collaboratively with design engineers to resolve them efficiently.
  • Automated Verification Tools: Utilize and enhance automated verification tools and scripts to improve efficiency and coverage, streamlining the verification process.
  • Mentorship: Provide technical guidance and mentor junior verification engineers, promoting a culture of continuous learning and improvement.
Requirements
  • UVM and Constraint Random Environments: Solid understanding of UVM and constraint random environments.
  • Verification Planning and Management Methods: Skilled in verification planning and management methods.
  • SystemVerilog and Verilog Experience: Excellent experience in SystemVerilog and Verilog, including formulating and writing SystemVerilog coverage statements.
  • Experience with Silicon IP Testing: Proven experience in creating testbenches for and testing of silicon IP.
  • EDA Simulation Tools: Familiarity with EDA simulation tools, including Questa, VCS, or Xcelium.
  • Metric Driven Verification Methodology: Experience with Metric Driven Verification methodology.
  • Teamwork and Pressure: Ability to work effectively as part of a team and under pressure.
Nice to Have
  • SVA Assertions: Familiarity with SVA assertions or similar.
  • IC Design and Implementation: Knowledge of IC design and implementation.
  • Formal Verification Techniques and Tools: Experience in Formal Verification Techniques and Tools.
Benefits

We offer a competitive salary of approximately $120,000 per year, depending on experience, and a range of benefits, including equal opportunities, flexible working arrangements, and professional development opportunities.

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