Senior ASIC Digital Design Engineer

vor 4 Wochen

Munich, Bayern, Deutschland Synopsys Vollzeit
Job Title: Senior ASIC Digital Design Engineer

Join Synopsys, a leader in silicon IP solutions, as a Senior ASIC Digital Design Engineer. We are seeking an experienced professional to join our team and contribute to the development of innovative digital IP solutions.

About the Role

We are looking for a highly skilled and motivated individual to work on the development and architecture of IPs verification solutions. As a Senior ASIC Digital Design Engineer, you will be responsible for:

  • Defining verification requirements with the design team
  • Developing test plans from specification documents
  • Writing UVM verification test bench architecture, agents, and test sequences
  • Reviewing test plans and verification code
  • Implementing SVA for functional and formal verification
  • Implementing coverage and reviewing coverage results
Key Qualifications

To be successful in this role, you will need:

  • 10+ years' relevant experience in digital design and verification
  • Experience with Verilog/System Verilog coding and simulation tools
  • Understanding of verification methodologies (UVM/OVM/SPECMAN)
  • Programming skills in C, System Verilog, TCL, Perl, or Python
  • Excellent communication and problem-solving skills
About Synopsys

Synopsys is a global leader in silicon IP solutions, providing a broad portfolio of predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. Our solutions help customers integrate more capabilities into their SoCs, faster, and with reduced risk.

We are committed to innovation and excellence, and we are looking for talented individuals who share our passion for technology and our commitment to excellence.

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