Senior ASIC Digital Design Engineer
vor 1 Woche
The Senior ASIC Digital Design Engineer is responsible for generating and verifying high-quality RTL design for the Synopsys High-Speed Ethernet DesignWare IP. The work involves block and function definition, detailed specification, RTL coding, and code verification.
Key Responsibilities:- Collaborate with the Design and Verification Team to write test plans and troubleshoot RTL code.
- Support Lint, CDC, Synthesis, and physical design activities to meet quality and performance requirements for ASIC IPs.
- Excellent knowledge of RTL Verilog and System Verilog Language, coding, and code simulation techniques.
- Experience in Ethernet system design.
- Knowledge of UVM to support the Design Verification Team.
Synopsys is a leading provider of silicon IP and design solutions. Our Silicon IP business integrates more capabilities into an SoC—faster. We offer the world's broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors.
Our goal is to help customers integrate more capabilities into their target applications, meeting unique performance, power, and size requirements. We enable customers to get differentiated products to market quickly with reduced risk.
About the RoleThis role is part of our Engineering team in Germany. We are looking for a highly skilled Senior ASIC Digital Design Engineer to join our team.
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Senior ASIC Digital Design Engineer
vor 1 Tag
Munich, Bayern, Deutschland Synopsys VollzeitJob DescriptionThe Senior ASIC Digital Design Engineer will be responsible for generating and verifying high-quality RTL design for the Synopsys High Speed Ethernet DesignWare IP.Key Responsibilities:Develop and verify RTL design for Ethernet system designCollaborate with the Design and Verification Team to write test plans and troubleshoot RTL codeSupport...
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Senior ASIC Digital Design Engineer
vor 1 Tag
Munich, Bayern, Deutschland Synopsys VollzeitJob DescriptionThe Senior ASIC Digital Design Engineer will be responsible for generating and verifying high-quality RTL design for the Synopsys High Speed Ethernet DesignWare IP.Key Responsibilities:Develop and verify RTL design for Ethernet system designCollaborate with the Design and Verification Team to write test plans and troubleshoot RTL codeSupport...
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Senior ASIC Digital Design Engineer
vor 21 Stunden
Munich, Bayern, Deutschland Synopsys VollzeitJob DescriptionThe Senior ASIC Digital Design Engineer will be responsible for generating and verifying high-quality RTL design for the Synopsys High Speed Ethernet DesignWare IP.Key Responsibilities:Develop and verify RTL design for Ethernet system designCollaborate with the Design and Verification Team to write test plans and troubleshoot RTL codeSupport...
-
Senior ASIC Digital Design Engineer
vor 21 Stunden
Munich, Bayern, Deutschland Synopsys VollzeitJob DescriptionThe Senior ASIC Digital Design Engineer will be responsible for generating and verifying high-quality RTL design for the Synopsys High Speed Ethernet DesignWare IP.Key Responsibilities:Develop and verify RTL design for Ethernet system designCollaborate with the Design and Verification Team to write test plans and troubleshoot RTL codeSupport...
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