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Senior ASIC Digital Design Engineer

vor 2 Monaten


Munich, Bayern, Deutschland Synopsys Vollzeit
Job Description

The Senior ASIC Digital Design Engineer will be responsible for generating and verifying high-quality RTL design for the Synopsys High Speed Ethernet DesignWare IP.

Key Responsibilities:
  • Develop and verify RTL design for Ethernet system design
  • Collaborate with the Design and Verification Team to write test plans and troubleshoot RTL code
  • Support Lint, CDC, Synthesis, and physical design activities to meet quality and performance requirements
Requirements:
  • Excellent knowledge of RTL Verilog and System Verilog Language, coding, and code simulation techniques
  • Experience in Ethernet system design
  • Knowledge of UVM to support the Design Verification Team
About Synopsys

Synopsys is a leader in silicon IP and software security solutions. We empower innovators to create products that change the world. Our technologies enable the development of advanced semiconductor chips and software that drive innovation in industries such as artificial intelligence, 5G, and the Internet of Things.

We are committed to creating an inclusive and diverse work environment where everyone has the opportunity to succeed. We believe that diversity and inclusion are essential to our success and the success of our customers.