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Principal AMS Verification Engineer
Vor 4 Tagen
Are you excited about R&D? An R&D Centre in Munich is looking for an experienced AMS Verification Engineer to work full time in their office (no hybrid working).
International candidates with strong skills in System C, System Verilog, Verilog A will be considered and visa can be provided for an exceptional candidate.
A competitive salary package including a bonus will be offered.In your role you will have the following responsibilities:
System level model development for analog/mixed signal ASIC/IP according to both application and circuit design requirementsImplementation of user cases, fault injection and simulation test bench for analog system design verificationMaintenance and quality assurance for analog system models' accuracy, scalability and reusabilityWork with CAD group to improve the mixed signal verification methodologyAnalog/ mixed signal fault modeling and simulationRequirementsSuccessfully completed Master or PhD.
degree in Electrical Engineering, Microelectronics or any related fields of study and ideally experience in an R&D environmentIndustry experience in analog/ mixed signal behavior modeling (e.g. System C, System verilog, Verilog A)Knowledge or hands-on experience in analog/mixed circuit design (e.g. LDO, Buck, ADC, PLL)Experience of analog/mixed signal design verificationFor more information and to apply, please contact Molly at IC Resources with your CV and a time for an initial call.-
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