Analog Ic Layout Design Internship

vor 1 Woche

Munich, Bayern, Deutschland Renesas Electronics Vollzeit

Company Description
Renesas is one of the top global semiconductor companies in the world.

We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets.

Our robust product portfolio includes world leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products.

We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.

Renesas employs roughly 21,000 people in more than 30 countries worldwide.

As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements:
Transparent, Agile, Global, Innovative, and Entrepreneurial.

Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values.

At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what's next in electronics and the world.

Job Description We are looking for an Intern / Working Student / (F/M/D) for our Analog Layout Design Team.**Job Responsibilities:
  • Projects delivery with other layout and circuit design engineers to resolve any technical issues that will affect layout to ensure high quality.
  • Utilize EDA tools (Cadence and Synopsys) for layout design and all related verification items, perform all layout activities as cell and block level creation, edit and full verification.
  • Use stateoftheart layout techniques for matching, ESD, latchup prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
  • Attending all relevant project meetings, continuous assessment and reporting of timescale risks.
  • Where possible, use schematic driven layout and consider top level auto routing.
  • Involve in review session and prepare all related document and data preparation for wafer tape out.

OUR OFFER

  • Working close with your mentor
  • Flexible working hours
  • Flat hierarchies
  • Interaction with international locations
  • Good public transportation connections
  • Attractive compensation

Qualifications

  • Student in Electrical/Electronic, Physics, Computer or related fields.
  • Must have good verbal and written communication skills in English.
  • Good understanding of integrated analog circuit design.
  • Good understanding of chip layout in cell and block level creation, edit and full verification.
  • Highly selfmotivated and adaptable.
  • Having the basic knowledge of CMOS related devises including high voltage and the skill of deciphering Design Manual.

Nice to have:

  • Experience with layout techniques for matching, ESD, latchup prevention and parasitic reduction and work with an awareness and understanding of the process from physical point of view.
  • Experience in analog IC/ mixed signals IC layout designs and verifications. Able to perform with ideas on chip size reduction.

Additional Information
Renesas' mission, To Make Our Lives Easier, is underpinned by our company culture, TAGIE. TAGIE stands for Transparent, Agile, Global, Innovative and Entrepreneurial.

Our goal is to embed this unique culture in everything we do to succeed as a company and create trust with our diverse colleagues, customers and stakeholders.


Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law.

For more information, please read our Diversity & Inclusion Statement.

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