Senior SoC Digital Verification Engineer
vor 3 Wochen
Your responsibilities will include the following:
- Development of verification specifications and plans for complex SoCs
- Leading verification efforts on module, cluster and toplevel
- Implementing UVM environments for functional, netlist and power simulations
- Developing reusable verification IP using the UVM framework
- Developing reference models using System Verilog / Matlab / Python
- Improving verification flow and methodology
- Debugging design modules using state-of-the-art simulation and formal tool and methods
- Collaborating with system engineers on post-silicon debug and device bring-up in the lab
- Master’s degree (Dipl.-Ing.) or PhD in electrical engineering or computer science and 10+ years of experience in verification of complex SoC designs
- Excellent skills in System Verilog and SVA
- Excellent knowledge of metric driven verification methodology and flow
- Broad expertise in development of SV/UVM environments for complex SoCs
- Excellent knowledge of state-of-the-art simulation and formal tools (Cadence/Synopsys)
- Good skills in Matlab, Python, Perl
- Excellent written and verbal communication skills in English both internal and client-facing
- Willingness to travel occasionally
For more information and to apply, please contact Lucy with your CV and a time for an initial call.
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