Early Careers SOC Physical Design Engineer

vor 2 Wochen

Munich, Bayern, Deutschland Apple Vollzeit 80.000 € - 120.000 € pro Jahr
Imagine what you could do here. At Apple, new insights have a way of becoming phenomenal products very quickly. There's no telling what you could accomplish at Apple.

As a Physical Design Engineer, you will take part in the large scale physical design cycle from netlist to tape-out, including full flow of back-end implementation & verification always meeting schedule and design goals. By now the industry is accustomed to Apple taping out the SoCs for our various products at a rigorous pace. In order to achieve this, our world-class design processes are driven by our outstanding Physical Design engineers. Are you ready to join some of the world's leading engineers and help us deliver the next generation of ground-breaking Apple products?

Description
As a member of our Physical Design team in this highly transparent role, you will directly own implementation of design partition(s) (netlist to delivery of our final GDS) for a highly complex SoC utilizing state of the art process technology; Responsibilities include especially, but are not limited to:
- You are going to own block level PnR, floor-planning, clock and power distribution;
- You will get involved with static timing closure with commercial tools;
- You will do power and noise analysis (EM / IR-Drop / Xtalk) as well as layout verification (DRC / LVS);
- You will be developing and validating high performance low power clock network guidelines;
- With phenomenal focus you will resolve design and flow issues related to physical design, and identify potential solutions whilst driving execution;
- You know what documentation should look like, and will help with guidelines and specs.

Minimum Qualifications
We will be counting on your expertise and hands on experience with one of the Place & Route ('PnR') tools available today (Synopsys /Cadence), and having understanding of their capabilities and underlying algorithms.
You are familiar with hierarchical design approach, top-down design and timing & physical convergence.
You demonstrate an understanding of static-timing analysis, know-how in clock/power distribution and analysis, as well as RC extraction and correlation.
You have experience with SoC practices such as multiple voltage and clock domains, integration of mixed-signal IPs & I/O integration.
You can do scripting and programming using several of the following: Perl, TCL and Make.
Ability to fluently speak and write in English.

Preferred Qualifications
Solid understanding in Verilog is beneficial.
Experience with large SoC designs.

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