Ph.d. Candidate

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This Ph.D. research focuses on developing advanced fault models and safety verification techniques for AI accelerators using cutting-edge EDA tools. The research will involve exploring safety analysis methodologies using functional testing techniques or metric-driven verification methodologies tailored to AI accelerators. Additionally, the project will exploit and optimize safety verification techniques, such as simulation-based fault injection and formal verification, to enhance the safety of AI accelerators. The solutions developed will be integrated into the overall Cadence Functional Safety tool flow, resulting in an advanced methodology that improves safety verification processes and accelerates the time-to-market for AI accelerator design.

Specific background:

- M.Sc. (or equivalent) in Electrical Engineering, Computer Engineering, Computer Science, or related areas
- Understanding of digital integrated circuit digital design & verification flows and tools
- Knowledge of hardware design languages (Verilog, VHDL) and programming skills
- Theoretical background in Functional Safety is preferred.

Requirements:

- The applicant must fulfil the eligibility rules mentioned on the project website

Benefits we offer you:

- Competitive Salary
- 30 days annual leave
- Meal vouchers
- Capital Forming Payment (VwL)
- Ticket for the public transport
- Working in a hybrid model in a modern office concept

And so much more, do not hesitate to contact us.

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