Sta Lead

**Description**

As a Lead of a local Timing team, you will be responsible for all aspects of SoC design in terms of timing and synthesis. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will also closely collaborate with RTL designers to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical Design team to close and sign-off timing. You will come up with ideas and plans to verify timing constraints, innovate timing constraints and flow to facilitate timing closure, improve synthesis result, improve methodologies and ensure that your team delivers the required collaterals in time with high quality.

**Minimum Qualifications**
- We look forward to hearing your detailed knowledge of the ASIC design timing closure flow and methodology, as this role requires. Ideally, you will have:

- Relevant years of experience in writing ASIC timing constraints and timing closure.
- Validated experiences in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations & signal integrity related issues.
- Hands-on experiences in timing/SDC constraints generation and management.
- Proficient in scripting languages (Tcl and Perl).
- Have good knowledge in synthesis, DFT and backend-related methodology and tools.
- Excellent communication and interpersonal skills and always enthusiastic to collaborate with diverse teams.
- Ability to work well in an international team, take responsibility, perform under strict deadlines and motivate self to balance priorities.
- Relevant experience in managing technical teams, ideally in the area of ASIC design.
- Proficiency in English language is required

**Preferred Qualifications**

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