Doctoral Researcher: Physical Features and Constraints in Digital IP-Generation

vor 4 Wochen


Munich, Bayern, Deutschland Infineon Technologies Vollzeit
Research Opportunity at Infineon Technologies

We are seeking a highly motivated and skilled researcher to join our team at Infineon Technologies. As a doctoral researcher, you will have the opportunity to work on a cutting-edge project that focuses on enhancing digital IPs with physical awareness.

The project aims to overcome the barrier of technology-independent RTL code and technology-dependent features by making RTL generators aware of physical features. You will be responsible for extending IP-metadata with timing and power information and constraints, generating timing constraint files and UPF, and establishing a feedback loop.

This is an excellent opportunity to gain hands-on experience in digital hardware design and implementation, methodology of code generation in an industrial environment, modeling and meta-modeling, and various modeling and abstraction concepts.

As a researcher at Infineon Technologies, you will have access to our vast network of doctoral candidates and the expertise of a university. You will also have the opportunity to collaborate with colleagues and teams that are seldom found anywhere in the world in terms of depth and breadth.

We offer a wide range of benefits, including coaching, mentoring, and networking possibilities, as well as a flexible working environment with home office options and part-time work possible.

Requirements:

  • Graduated in computer engineering, electrical engineering, or a related field with very good grades
  • Interested in complex, interdisciplinary, and interlinked tasks and willing to solve them together with colleagues
  • Possess good presentation skills that help you to present challenging issues clearly and simply
  • Curious and open as well as interested in learning and trying out new things
  • Have first experience with metamodeling, (template-based) code generation, and/or model-driven architecture
  • Possess knowledge in object-oriented programming with languages such as C++ or Python
  • Have good knowledge of digital design and RTL modeling in VHDL and/or (System)Verilog and embedded system architectures
  • Have good knowledge in synthesis and layout tools
  • Interested in generation and recursive application of generation, generation of generators
  • Possess very good language skills in English and ideally German


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