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Digital Verification Expert

vor 2 Monaten


Munich, Bayern, Deutschland Albelissa Vollzeit

About the Role

Albelissa is seeking a highly skilled Digital Verification Engineer to join our team in Germany. As a key member of our engineering team, you will be responsible for defining verification strategies for digital and mixed-signal IPs, developing efficient and reusable verification environments, and interacting with design engineers to ensure feature extraction.

Key Responsibilities

  • Develop and implement verification plans, including testbench architecture and partition, to ensure comprehensive coverage and re-use.
  • Apply state-of-the-art methodologies, such as UVM and Formal Verification, to develop efficient and reusable verification environments and testbench components.
  • Define infrastructure to support mixed-signal verification and analog/real-number behavioral modeling.
  • Support the execution of verification plans, including environment setup, regression running, coverage collection, and failure debug.
  • Collaborate with customers and other work-packages to ensure schedule adherence and interactive problem-solving.
  • Mentor junior engineers to learn required knowledge and experience through project work.

Requirements

  • Master's degree in Electrical Engineering with 7 years of experience or Bachelor's degree with 10 years of experience, with an emphasis in Digital Verification or a similar specialty.
  • Expertise in digital verification, including testbench architecture and verification planning, and execution of digital and mixed-signal designs.
  • Expertise in IPs (block-level) and integrated systems (top-level) verification with reusable components and coverage models.
  • Expertise in SystemVerilog for verification using advanced verification methodologies, including constrained random and metric-driven verification.
  • Experience in Formal verification.
  • Experience with EDA tools used for simulation, regressions, feature extraction, and verification planning.
  • Knowledge of scripting languages, such as Python, Tcl, and Perl, for automation and code generation.
  • Fluent in English.
  • Excellent team player with a calm professional demeanor and excellent listening skills, ability to organize and prioritize work.

Preferred Skills

  • University degree in Electrical Engineering + 7+ years of experience
  • Bachelor degree + 10+ years of experience
  • Emphasis in Digital Verification
  • Testbench architecture and verification planning
  • Digital and mixed-signal designs
  • IPs (block-level) and integrated systems (top-level) verification
  • SystemVerilog (UVM, SVA or similar), including constrained random and metric-driven verification
  • Experience in Formal verification
  • EDA tools
  • System Verilog RNM and analog
  • Python, Tcl, Perl
  • English fluency