Senior Engineer for Digital Verification

vor 4 Wochen

Dresden, Sachsen, Deutschland Arbeitgeber aus der Region Vollzeit
Join Our Team as a Senior Engineer for Digital Verification

Are you ready to take your career to the next level? We invite you to become a part of our "Design Enabling and Services" team in Dresden as a Senior Engineer specializing in Digital Verification (f/m/div). In this role, you will enhance your skills in areas that demand high security and safety standards while engaging in verification initiatives across all divisions of our organization globally.

As you contribute your expertise, you will also have the opportunity to cultivate a professional network across various sites and departments. By continuously expanding your knowledge and tackling complex challenges, you will establish yourself as a thought leader, playing a crucial role in refining our products to make a positive impact on the world.

Your Key Responsibilities:
  • Lead a diverse team focused on verification tasks.
  • Develop and outline verification strategies for specific projects and modules.
  • Construct the verification environment for integrated circuits utilizing the "Universal Verification Methodology" (UVM).
  • Design test scenarios using SystemVerilog and Specman E, verifying functionality through a "Constrained Random" methodology.
  • Create assertions in SystemVerilog for formal verification processes.
  • Collaborate with other teams, such as Concept and Application Engineering, to establish verification methodologies and plans based on project requirements.
  • Conduct verification of intricate integrated circuits and products to identify design flaws and troubleshoot issues.
Your Profile:

You are well-suited for this position if you possess:

  • A university degree in electrical engineering, computer science, or a related field.
  • A minimum of 3 years of experience in Metric Driven Verification (digital and/or mixed-signal).
  • Knowledge and experience with microcontroller-based integrated circuits, alongside security and safety protocols.
  • Strong expertise in UVM, particularly with SystemVerilog.
  • Familiarity with firmware and RTL design (VHDL).
  • Experience using Cadence verification tools.
  • Proficiency in English; German language skills are an advantage.

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