Analog/Digital Design Engineer Internship

vor 2 Wochen

Dresden, Sachsen, Deutschland Renesas Electronics Vollzeit

Renesas Electronics is seeking a highly motivated and talented Working Student / Master Thesis Student (F/M/D) specializing in Analog or Digital design or Functional verification to join our dynamic R&D team within the Connectivity Sensor Division.

We are dedicated to enhancing people's lives by developing cutting-edge products. The Silicon Engineering team is looking for an individual who is passionate about analog/digital design techniques, functional verification, and creating innovative technologies.

Your Responsibilities
  • Participate in analog/digital block design or verification processes
  • Develop testbenches and modeling strategies (analog/digital simulation/UVM & verification components/top-level AMS verification using UVM framework)
  • Conduct simulation and verification activities to validate design performance and use cases in verification plans
  • Establish automated regression flows and efficiently document/organize project outcomes
  • Explore possibilities for production/bench-level test plans
  • Provide support during the lab evaluation phase
What We Offer
  • Work closely with a dedicated mentor
  • Enjoy flexible working hours
  • Engage with international teams
  • Benefit from an attractive compensation package
Your Qualifications
  • Currently pursuing a Master's degree in Electrical Engineering or equivalent
  • Understanding of device physics relevant to IC designs
  • Some knowledge of analog/digital IC design flow, tools, or verification processes (schematic entry/simulation or RTL coding using Verilog/System Verilog/VHDL or UVM-based verification)
  • Experience with industry-standard simulation tools and initial bench evaluation exposure
  • Strong written and verbal communication skills
  • Ability to collaborate within international teams
  • Availability for a minimum of 4 months full-time (40 hours per week) or at least 6 months part-time (20 hours per week)

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