Research Associate for Secure Chip Design

Vor 6 Tagen


Garching bei München, Bayern, Deutschland Fraunhofer-Gesellschaft Vollzeit
About the Role

We are seeking a highly skilled Research Associate to join our team at the Fraunhofer Institute for Applied and Integrated Security AISEC. As a key member of our Hardware Security Department, you will be responsible for designing and developing secure chip architectures based on the RISC-V instruction set.

Key Responsibilities
  • Design and implement secure chip architectures for embedded systems
  • Develop and integrate hardware and firmware for FPGAs and microcontrollers
  • Design and analyze analog circuits, systems, and algorithms for Physical Unclonable Functions, tamper detection, and hardware fingerprinting
  • Conduct side-channel and fault analyses in our hardware security lab
  • Publish scientific results and collaborate with international partners
Requirements
  • Master's degree in Electrical and Computer Engineering, IT Security, Computer Science, or a related field
  • Strong background in digital design, analog design, electronic measurements, or a related field
  • Experience with RISC-V instruction sets and architectures preferred
  • Excellent communication skills in German (B2 level or higher)
What We Offer

As a Research Associate at Fraunhofer AISEC, you will have the opportunity to work on cutting-edge research projects, collaborate with international partners, and publish your scientific results. We offer a dynamic and inclusive work environment, with a focus on diversity and equal opportunities.

We value your skills and experience and look forward to receiving your application.



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