Research Associate for Secure Chip Design

vor 1 Tag


Garching bei München, Bayern, Deutschland Fraunhofer-Gesellschaft Vollzeit
About the Role

We are seeking a highly skilled Research Associate to join our Hardware Security Department at Fraunhofer AISEC. As a key member of our team, you will be responsible for designing and developing secure chip architectures based on the RISC-V instruction set.

Key Responsibilities
  • Design and implement secure chip architectures for embedded systems
  • Develop and integrate hardware and firmware for FPGAs and microcontrollers
  • Design and analyze analog circuits, systems, and algorithms for Physical Unclonable Functions, tamper detection, and hardware fingerprinting
  • Conduct side-channel and fault analyses in our hardware security lab
  • Publish scientific results and collaborate with international partners
Requirements
  • Master's degree in Electrical and Computer Engineering, IT Security, Computer Science, or a related field
  • Background in digital design, analog design, hardware software co-design, FPGA design, electronic measurements, circuit design, or communications engineering
  • Experience with current instruction sets and architectures of embedded processors (RISC-V preferred)
  • German communication skills (B2 level)
What We Offer

As a Research Associate at Fraunhofer AISEC, you will have the opportunity to work on cutting-edge research projects, collaborate with international partners, and publish scientific results. We offer a dynamic and inclusive work environment, with a focus on diversity and equal opportunities.

We value your skills, experience, and passion for secure chip design. If you are a motivated and talented individual looking to contribute to the development of secure embedded systems, we encourage you to apply for this exciting opportunity.



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