Doctoral Thesis: Detection and Recovery Mechanisms
vor 1 Woche
This thesis aims to develop detection and recovery mechanisms for analog devices in edge AI hardware. It will evaluate mechanisms that can be integrated into analog edge AI platforms to improve their reliability and safety. Due to the different nature of analog circuits, the intended solutions for digital edge AI platforms (DC1.4) cannot usually be reused, except for passing deviation information to higher-level functionalities. In-field mechanisms that can detect or compensate for relevant deviations of circuit-specific parameters or performances will be developed. Similar to DC1.4, mechanisms to stress the analog hardware or emulate relevant stress will be implemented to enable verification of the developed assessment methods.
The thesis will be written in cooperation with Taltech University and under the supervision of professor Maksim Jenihhin.
**The tasks within the thesis will consist of:
**- Development of **low/zero overhead mechanisms **that can be integrated in **digital edge AI platforms **in order to improve the overall reliability and safety
- Investigation of **dedicated mechanisms **to facilitate the evaluation and the assessment of hardware health, e.g., the number of occurred bit-flips or wrong computation results
- Exploration of **in-field, run-time monitoring techniques of hardware health **, and **mechanisms to collect error measurements **by using functional communication units, e.g. on-chip busses for system evaluations
- Development of **schemes to ensure reliability by design **and **by activating in-field mechanisms **which ensure the intended functionality or recover the hardware
- Implementation of **mechanisms to stress the hardware **or to **emulate a relevant stress **to enable a thorough verification of the various assessment methods for the hardware health
- Evaluation of these solutions **on real chips **and **under stress of atomic particles
**Your Profile**:
A doctoral student is a **research enthusiast **,
›who enjoys working in an industrial environment in combination with an Infineon partner university.
›who appreciates open communication and the contribution of an international environment.
- Have **not been working or studying in Germany for more than 12 months in the last 36 months**
- Are **eligible for full-time PhD studies **and have a master’s degree in **Computer Engineering, Electrical Engineering **or a related field with **very good grades**:
- Are interested in **complex, interdisciplinary and interlinked tasks **and should like to solve them together with colleagues
- Possess good **presentation skills **, helping you to present challenging issues **clearly and simply**:
- Gained **first experience with metamodeling **, (template-based) **code generation **and/or **model-driven architecture**:
- Have knowledge in **object-oriented programming **with languages such as C **++ and Python **and **embedded programming **with C and/or Assembler
- Possess good knowledge of **digital design and RTL modeling **in VHDL and/or (System)Verilog and embedded system architectures
- Possess **very good language **skills in **English and ideally German**
- CV in English
- Cover LetterLatest grades transcript from univeristy
**Contact**:
Sophia Dechant
**#WeAreIn for driving decarbonization and digitalization.**
As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.
**Are you in?**
The central R&D organization **„Design Enabling and Services“ (DES) **provides the design environments (design-systems) to the different product development teams at Infineon. With leading edge design methods, complex building blocks and a wide range of product development services DES enables Infineon's advanced IC development. This means the complete value creation chain from abstract system models down to the fully verified product layout which ensures high quality manufacturing readiness.
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