Master Thesis
vor 5 Monaten
**Your Job**:
You will have the chance to work together with us on this major challenge by developing an ultra-low power comparator to readout the state of a qubit. To reach the required precision, you will implement a novel digital calibration loop for the comparator and benchmark it to existing analog calibration concepts.
The specific tasks are to design, layout and verify an ultra-low power, low noise comparator with a digital calibration loop:
- Analog Design and simulation of a dynamic comparator and a DAC
- Digital design and simulation of a calibration logic
- Mixed-Mode Simulation to evaluate the overall performance of the design
- Layout and aprasitic extractions of the analog calibration loop
- Comparison to existing comparators with analog calibration
**Your Profile**:
- Enrolled in an M. Sc. course at a European university for Electrical Engineering, Physics or similar fields
- Experience with analog circuit design and the Cadence analog design enviroment as well as SPICE simulations
- First experience with in full custom layout for state of the art technologies is a plus
- Knowledge of digital circuit description (Verilog or VHDL)
- Good English capabilities and optionally knowledge of German
**Our Offer**:
We work on the very latest issues that impact our society and are offering you the chance to actively help in shaping the change We support you in your work with:
- Opportunity to work on highly-relevant engineering challenges with state of the art technologies
- Continuous scientific mentoring by your scientific advisor as well as a close integration in the international research group
- Being involved in various steps of the development flow for an integrated circuit
- Excellent scientific and technical infrastructure
- Flexible work hours and the possibility to partially work from home
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