Ams Design Verification
vor 3 Monaten
**Summary**
Posted: 9. Sep 2024
Weekly Hours**:40**
Role Number**:200549109**
Do your life’s best work here at Apple This role is for a Design Verification engineer who will enable bug-free first silicon for the mixed-signal designs in our Munich team. The responsibilities include all phases of pre-silicon verification including but not limited to: construction of verification environments, coding of test scenarios and assertions and close collaboration with Analog and Digital Design engineers.
**Description**
Definition and design of Self-checking verification environments for multi-layer systems using the SystemVerilog UVM library. The responsibility spans from concept discussions, verification strategy definition and execution of the verification tasks to ensure bug-free tape-outs. The AMS DV engineer goes beyond standard verification techniques and include: - performance-based analysis - power related analysis and scenario design for early power estimation - deliveries of test for design for test and test engineering teams - gate-level verification (power and timing) - lab bring-up support A significant part of the AMS DV team focuses on research and innovations to improve verification techniques and tools for mixed-signal systems in order to increase efficiency and quality. Looking forward and establishing cutting edge concepts and methods to support them are part of the AMS DV team’s DNA.
- Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
- Basic design background in support of verification results analysis
- Knowledge of Object Oriented Programming (OOP)Proficiency in English language is required
**Preferred Qualifications**
English - US Language
**Additional Requirements**
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