Intern - Digital Design Verification (F/m/d)
vor 3 Monaten
**Your responsibilities**:
- Develop key Design Verification skills that are relevant to the semiconductor industry.
- You will be given guidance on what to do, and the freedom to plan and manage your own time.
- Your tasks will include documentation, coding, and debugging of digital designs.
- Assist in creation of verification plans for ASICs on system/block level.
- Assist in development of verification environments using object-oriented techniques (UVM methodology)
- Assist in development of SystemVerilog assertions and verification of design blocks using formal verification methods.
- Set up and run regressions to attain the verification goals.
**Your profile**:
- Working towards a bachelor’s or master’s degree in electrical engineering, computer engineering or similar
- Good understanding of concepts relevant for software development, digital design, and verification
- Strong analytical and problem-solving skills, willing to learn and ready to take on problems.
- University project experience of digital design using VHDL, Verilog or SystemVerilog
- Knowledge of programming languages such as C, C++ or Python
- Excellent communication skills (including English)
- Well organized, adaptive working style and paying attention to detail.
- Team player and eager to develop best in class products.
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