DFT Engineer

DFT Engineer

In this role, you are responsible for working with multi-site teams to drive the design implementation, simulations, and to successful tape-outs.

Key Responsibilities:

• Driving the DFT architectures, methodologies and tool flows for complex multi-million gate designs with Analog/high bandwidth SerDes designs
• Good understanding of ATE, Wafer bring up debug issues and drive the test engineering team for successful Silicon bring up and test program development
• Define the test plan by closely working with the team and developing functional/structural tests for final/wafer test program development
• Closely work with the team in defining HTOL test suite/cycle times/bring up on burn-in PCB boards
• Knowledge of lab bench Silicon debug, Characterization

Qualifications:

• 5+ years of DFT experience including architecture specification, implementation, test pattern development, and verification
• Experience with MBIST insertion, simulation, and verification on RTL and Gate Level Netlist
• Experience with Scan insertion, Scan compression, Stuck-At, At-Speed test, and coverage analysis
• Scan ATPG pattern generation, simulation, and debug on RTL and Gate Level Netlist
• Hands-on knowledge in state-of-the-art EDA tools for DFT, design, and verification (Mentor, Cadence, Synopsys)
• STA DFT Test mode timing constraint development and analysis
• In-depth knowledge of Verilog HDL and experience with simulators and waveform debugging tools
• TCL scripting; Python scripting is a plus
• Bachelor Degree minimum required in Electronics or other related fields